Chipworks Corner

A regular series of device-level process analyses, written exclusively for MICRO by Chipworks' senior technology adviser, Dick James.

TSMC fabbed Matrix 3-D memory array with unique 0.15- μm, seven-metal process
(June 2006)

Infineon uses vertical structure to optimize on-resistance in power MOS devices
(April 2006)

Fujifilm Maximizes Charge-Coupled Device’s 0.35-µm, Two-Metal, Double-Poly Process
(January/February 2006)

Texas Instruments Pushes MEMS Envelope with Micromirror-Based DLP
(October/November 2005)