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NO IDLE THREAT: Process complexities below 180 nm are causing a rise in yield loss from systematic failures, start-up's founder says. SOURCE: PETERSEN ADVANCED LITHOGRAPHY

The semiconductor industry is heading for a train wreck, warns John Petersen. The cause? Systematic failures "where the design and the process have a mismatch." The result? Yield hits and idle lines caused by processes running at much less than their full potential.

Petersen, a former fellow at International Sematech, asserts that the bulk of these mismatches occur in lithography. He acknowledges the industry is debating the extent that problems can be traced to lithography, or to the interaction of lithography and layers. What is certain, though, is that the yield issues have become particularly acute at the sub–180-nm technology node, where interconnect wiring, structure, and gate uniformity contribute to performance problems, Petersen says.

His four-year-old firm, Petersen Advanced Lithography (PAL), has developed a "workbench" that uses number-crunching power of linked computers to solve design problems tied to this essential process step. Called ProLE, the lithography simulation and analysis software uses distributive computer power to solve design-for-manufacturing (DFM) problems tied to lithography.

More than 69 variables can affect lithographic yields, Petersen says. Tackling these problems requires an integrated approach, he argues. Making optical corrections based on mask type, wavelength, lenses, and illumination is not sufficient. In addition, fabs must take into account photoresist chemistry as well as substrates, process, and pattern transfer. Off-line experiments cost too much in both time and money.

The simulation models that Petersen and his team created are designed to provide accurate and rigorous models that measure and calibrate critical variables. These variables are combined in an overall image process integration tool. PAL's system encompasses the five components of the DFM world: electronic design automation (EDA), lithography and technical computer-aided design (TCAD), resolution extension technology (RET), photomasks, and the wafer fab.

Petersen demonstrated ProLE, which stands for "programmable lithography engine," at the 2002 SPIE Microlithography Conference in Santa Clara, CA. The simulation system uses KLA-Tencor's Prolith 3D v7.1.1. tool and other powerful analytical tools as part of "what we call a grid-based supercomputer to solve these immense problems that we deal with," Petersen says.

While doing contract work for Sematech, PAL also developed a mask called SCAA, or sidewall chrome alternating aperture mask, that solves a longstanding defect problem in the use of a strong phaseshift mask. "Most masks have a phase error that is dependent on the pitch of the mask," said Petersen during a recent interview at PAL's offices in Austin, TX. The mask has been made correctly, he notes, "and yet there was an apparent phase error."

The error is caused by "the corners of the cuts that make the phase diffract light and the way they interfere to create the phase. The beauty of the SCAA mask is that it doesn't have any of these problems.

"The way it shows as a defect is that, as focuses varied, the image would 'walk,'" Petersen continued. "If you can imagine two pitches side by side, in one focus condition one pitch would be small and in the other [focus condition] it would be big. As you go through focusing, it shifts. That's a huge problem. Well, SCAA doesn't have that problem. We see that as a real benefit to that technology."

Working with ASML Mask Tools and ASML, Petersen and his colleagues have also developed a technique called chromeless-phase lithography (CPL) for the 100- and 65-nm technology nodes. CPL is under evaluation, while SCAA will take longer to ramp up "because it's a harder technology to make the photomask."

PAL used ProLE to develop the SCAA mask. "I really believe from an optical standpoint we've developed, or been part of the development of, two of the key technologies" in this area.

In addition to developing these tools, PAL helps clients get to the root of poor yields. The PAL team has discovered the systematic failure trend that begins at the 180-nm node. "If we look at their designs, at first it looks like everything's okay, but when we do a focus exposure response, say, of their poly, and of their active [layer], and their contacts, and their metal, what we find is, first off, in order to get a good transistor the poly [layer] has to overlay the active in a certain way. We find it doesn't."

Using optical proximity correction may improve the overlay, Petersen points out. However, OPC "may have some harmful effect, layer to layer." To prevent this from happening PAL uses OPC on every layer "and then we overlay the layers to make sure that as the process varies there are no failures. Anyway, we have instances where we have taken yields that were literally 0% and [improved] them to 60%."

Petersen says the reason for the increase in systematic failures is the subject of much industry discussion. "The systematic failure is where the design and the process have a mismatch, in essence. The question then becomes how much of this mismatch is due to litho, how much is due to nonlitho issues? There's a lot of debate about that. Even though, I'd say a large portion of it is actually an interaction of the litho with the layers.

"That gives rise to very low-level yield loss in a part. Let's say you have, I don't know, 500 million transistors. Maybe 1% of those are showing this kind of systematic failure, or 0.2% of these are showing systematic failure. You go in there to examine it and you might see active and poly mismatches, or maybe endcaps on metals falling off of vias. Or the falloff could be because the via size is changing, and the metal size is wrong. There are all these variations.

"The net [problem] is: You get a nonworking bit cell, for instance. As the design problems are becoming more and more complex, this increase in systematic failures is occurring. What's happening in the industry is that designers are becoming leery of this, so they're doing a lot more 'guardbanding.' What I mean by that is they're putting a whole lot more slop into their design. What that does then is cause them to use less of the technology available to them to drive performance. The lack of knowledge of what's causing the failure is making people be more cautious."

The result, he agrees, is that chipmakers are not maximizing the potential of their processes. "The problem is that it's a locomotive heading toward a brick wall." Quoting market research statistics, Petersen says an idled $2-billion fab loses perhaps $1 million daily. Photomask sets cost nearly $1 million. Developing an advanced CPU costs in the range of $50 million "at the 90-nm node. And that price is increasing approximately 36% every technology node."

With so much at stake, Petersen warns that the issues require immediate attention. "If we don't take care of these problems it could be the difference between being in business and not being in business. That's always been the case, but it was nowhere near the magnitude that it is now."